The present invention relates to systems and methods for generating a clock signal.
To address the ever-increasing need to increase the speed of computers to process ever increasing amounts of data, computer designers have increased the clock frequency of a computers central processing unit and/or utilized parallel processing. Many electrical and computer applications and components have critical timing requirements that require clock waveforms that are precisely synchronized with a reference clock waveform. As discussed in U.S. Pat. No. 6,236,278, to generate a high frequency clock from a lower frequency reference clock, a phase-locked loop (“PLL”) is typically used to provide an output signal having a precisely controlled frequency that is synchronous with the frequency of a reference or input signal. In microprocessors, for example, an on-chip PLL can multiply the frequency of a low frequency input (off-chip) clock to generate a high frequency output clock that is precisely synchronized with the lower frequency external clock. Due to the high clock frequency, power consumption for each device has also increased. For certain products such as laptop or notebook computers, handheld computers, cellular telephones, and other wireless personal digital assistants that are designed for situations where power outlets are not available, the conservation of power can be important.
In a parallel trend, electronic devices that employ short-range radio links have found their way into the daily lives of many people within the past decade. Widespread applications include cordless phones, keyless entry for automobiles, garage door openers, and file transfer in portable computers. Current uses however, are in general restricted to single devices (two transceivers) or a group of very similar devices (e.g., laptop computers). Two recently initiated industry projects, Bluetooth and HomeRF, promise to broaden the use of wireless connections by specifying standard links for a wide range of electronic devices. Bluetooth and 802.11b radios utilize the publicly available 2.4 GHz ISM frequency band for transmission. Operation in this band does not incur usage fees or licenses and permits global use of Bluetooth and/or 802.11b devices.
Traditionally, multiple integrated circuit chips are required to implement systems offering wireless communications capability. To lower cost, a single chip implementation is needed. However, an integrated circuit with multiple input data ports, the proliferation of multiple phase locked loops and multiple reference clocks may unduly complicate the integrated circuit. Also, a typical digital clock produces a square wave signal in which the harmonics and sub-harmonics occur at the multiples of the clock frequency. With the clock frequency remaining the same, the harmonics are at the same frequency each cycle. These harmonics can interfere with the proper operation of analog components near digital components.